Recently, a latch circuit is usually structured by a CMOS circuit, for example, a general latch circuit is shown in FIG. 8 which is formed using an N type MOS transistor (NMT93, NMT94) connected between a power supply line (LVDD) supplied with a voltage VDD which is a predetermined voltage, and a power supply line (LGND) supplied with a voltage GND which is a ground voltage, and a p type MOS transistor (PMT95, PMT96).
In FIG. 9, the time change of a scanning voltage (φG), a drive clock (φAC) and each node (N91, N92, N93, N94) are shown.
First, the case where a voltage (data) on a data line (LD) is a Low level (below referred to as L level) voltage VL is explained.
As is shown in FIG. 9, when a scanning voltage (φG) on a scan line (LG) changes from an L level voltage VL to a High voltage (below referred to a H level) VH1 at time (t1), the n type MOS transistor (NMT91) is switched on and the voltage (data: voltage VL at time (t1)) on the data line (LD) is applied to a retention capacitance (CD). In this way, node (N91) becomes at the voltage VL.
Next, at time (t2), when the drive clock (φAC) on a latch control line (LAC) changes from a L level voltage VL to a H level voltage VH2, the n type MOS transistor (NMT92) is switched on and the node (N94) becomes at the voltage VL.
In this way, the p type MOS transistor (PMT95) and the n type MOS transistor (NMT94) are switched on, the p type MOS transistor (PMT96) and the n type MOS transistor (NMT93) are switched off, the node (N92), that is, second output (OUT2), becomes at a voltage GND, and the node (N93), that is, first output (OUT1), becomes at a voltage VDD. Therefore, the output of the first output (OUT1) becomes at a H level and the output of the second output (OUT2) becomes at a L level.
Next, the case where a voltage (data) on a data line (LD) is a H level voltage VDH is explained.
As is shown in FIG. 9, when a scanning voltage (φG) on a scan line (LG) changes from an L level voltage VL to a H level voltage VH1 at time (t3), the n type MOS transistor (NMT91) is switched on and the voltage (data: voltage VDH at time (t3)) on the data line (LD) is applied to a retention capacitance (CD). In this way, node (N91) becomes at the voltage VH3.
Next, at time (t4), when the drive clock (φAC) on a latch control line (LAC) changes from a L level voltage VL to a H level voltage VH2, the n type MOS transistor (NMT92) is switched on and the node (N94) becomes at the voltage VH4.
In this way, the n type MOS transistor (NMT93) and the p type MOS transistor (NMT96) are switched on, the p type MOS transistor (PMT95) and the n type MOS transistor (NMT94) are switched off, the node (N92), that is, second output (OUT2), becomes at a voltage VDD, and the node (N93), that is, first output (OUT1), becomes at a voltage GND. Therefore, the output of the first output (OUT1) becomes at a L level and the output of the second output (OUT2) becomes at a H level.
Furthermore, as is shown in FIG. 9, the voltages VDD and GND are fixed.
As an example of specific usage method of the latch circuit shown in FIG. 8, is the usage method shown in FIG. 10 whereby a pixel circuit of a display (below, referred to as movable shutter type display) which displays an image by electrically controlling the position of a movable shutter (S) using the two outputs (first output OUT1, second output OUT2) of the latch circuit. Furthermore, the movable shutter type display is also called a MEMS (Mechanical Electro Mechanical Systems) shutter type display. In addition, a movable shutter type display is disclosed in Patent Document 1 (Japanese Laid-Open Patent Publication No. 2008-197668) for example.
In the pixel circuit of the movable shutter type display shown in FIG. 10, the movable shutter (S) moves at a high speed in an electrical field direction. As a result, in the case where the node (N92) is a voltage GND, and the node (N93) is a voltage VDD, the movable shutter (S) moves to the node (N93) side, and in the case where the node (N92) is a voltage VDD, and the node (N93) is a voltage GND, the movable shutter (S) moves to the node (N92) side at a high speed.
In addition, the light emitting state and non-light emitting state of a pixel are controlled by opening and closing of the movable shutter (S). In a movable shutter type display which includes a back light, for example, in the case where the movable shutter (S) moves to the node (N92) side, the light of the back light becomes transmissive and a pixel becomes a light emitting state, and in the case where the movable shutter (S) moves to the node (N93) side, the light of the back light becomes non-transmissive and a pixel becomes a non-light emitting state.
In this way, in a liquid crystal display device, the same as an operation whereby a liquid crystal layer controls the output light, the movable shutter (S) controls the light output from a pixel and thereby it is possible to display an image. Furthermore, in FIG. 10, LSS is a movable shutter control line and φS is a movable shutter control signal. The movable shutter control signal (φS) is a predetermined fixed voltage. In addition, an s voltage is also possible, as in an inversion drive of a liquid crystal display device.
In the pixel circuit of the movable shutter type display shown in FIG. 10, data is programmed to each pixel in row units within a programming period (TA in FIG. 9), and the movable shutter (S) is moved to the node (N92) or node (N93) within a movable shutter state setting time period (TB in FIG. 9) and an image is displayed in the display time period (TC in FIG. 9).
A MOS transistor including polysilicon semiconductor layers is used in the case where a latch circuit is formed using a CMOS circuit as is shown in FIG. 8.
However, because a CMOS manufacturing process which uses a MOS transistor including polysilicon semiconductor layers usually requires six to ten photolithography processes, the structure of a latch circuit formed using a conventional CMOS circuit puts a significant burden on the manufacturing process. However, by using a single channel transistor structure for the CMOS circuit using either an n type MOS transistor or p type MOS transistor, it is possible to reduce to the number photolithography processes by about two and thus reduce the burden on the manufacturing process.
Furthermore, when a MOS transistor formed with amorphous silicon semiconductor layers is used, it is possible to further reduce process costs than in the case where a MOS transistor formed with polysilicon semiconductor layers is used.
The present invention was conceived based on the knowledge described above, and aims to provide a latch circuit and display device using the latch circuit which can reduce the burden on the manufacturing process. Furthermore, it is also an aim of the present invention to provide a single channel latch circuit which latches latch data in relatively short period intervals and a display device which uses the single channel latch circuit.
The aims of the present invention, other aims and new features will be made clear in the description of the present specification and attached diagrams.